`timescale 1ns / 1ps

module ProcessorTop_TestFixture;

	// Inputs
	reg rst;
	reg clk_100M_in;
	reg cpu_enable;

	// Outputs
	wire [31:0] out_reg_zero_value;
	wire [31:0] out_reg_t0_value;
	wire [31:0] out_reg_t1_value;
	wire [31:0] out_reg_t2_value;
	wire [31:0] out_reg_t3_value;
	wire [31:0] out_reg_ra_value;

	// Instantiate the Unit Under Test (UUT)
	Processor uut (
		.rst(rst), 
		.clk_100M_in(clk_100M_in), 
		.cpu_enable(cpu_enable), 
		.out_reg_zero_value(out_reg_zero_value), 
		.out_reg_t0_value(out_reg_t0_value), 
		.out_reg_t1_value(out_reg_t1_value), 
		.out_reg_t2_value(out_reg_t2_value), 
		.out_reg_t3_value(out_reg_t3_value),
		.out_reg_ra_value(out_reg_ra_value)
	);

	initial begin
		clk_100M_in = 1'b0;
		forever #5 clk_100M_in = ~clk_100M_in;
	end
	
	initial begin
		rst = 1'b1;
		cpu_enable = 1'b0;
		
		#30 rst = 1'b0;
		#20 rst = 1'b1;
		#50 cpu_enable = 1'b1;
		
		#2900 $stop;
	end
endmodule
